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[Other] 0340196Lab3

Description: 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
Platform: | Size: 484352 | Author: 王倩倩 | Hits:

[VHDL-FPGA-Verilog] 8BIT_CPU

Description: 一个8位的CPU设计，用verilog语言写的，希望有用-A CPU OF 8 BITS
Platform: | Size: 84992 | Author: 华云 | Hits:

[VHDL-FPGA-Verilog] A_CPU_verilog

Description: 这是一个verilog编写的CPU程序，希望对初学者有所帮组吧-a cpu
Platform: | Size: 770048 | Author: 华云 | Hits:

[assembly language] CACPU

Description: basic cpu design in verilog
Platform: | Size: 5120 | Author: ali231994 | Hits:

[VHDL-FPGA-Verilog] udp_send1

Description: 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Platform: | Size: 53248 | Author: qiubin | Hits:

[VHDL-FPGA-Verilog] mips

Description: Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Platform: | Size: 15360 | Author: DY | Hits:

[Other] sc_computer_2

Description: Verilog单周期CPU实现,可以实现简单的mips指令，附Verilog源码-Verilog achieve single-cycle CPU
Platform: | Size: 10116096 | Author: wangwei | Hits:

[VHDL-FPGA-Verilog] pcpu_handle_mem

Description: Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
Platform: | Size: 11389952 | Author: llly | Hits:

[VHDL-FPGA-Verilog] pic10

Description: 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好 PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考 PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test script code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test script file. Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks There are three documents: PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference PIC10F: PIC10 family of microcontrollers
Platform: | Size: 3458048 | Author: Eddie | Hits:

[MPI] m_cycle_mips

Description: verilog设计的5状态多周期mips -multiple cycle mips CPU design of Verilog
Platform: | Size: 11388928 | Author: 高杨 | Hits:

[VHDL-FPGA-Verilog] tinycpufiles

Description: TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is a Quartus project, and it can run well on Altera MAXII CPLD, and it is conveniently change to other FPGAs. The CPU used 200 Logical Cells, and the device (peripherals such as SPI, LCD) used 180 Logical Cells. It also included a assembler source code (by VC2008), which can compile the asm file for the CPU.
Platform: | Size: 60416 | Author: 肖海云 | Hits:

[Other] myCpu2

Description: CPU硬件实现，能运行基本程序，FPGA，verilog源码-CPU hardware implementation, can run the basic procedures, FPGA, Verilog source code
Platform: | Size: 5929984 | Author: 杨英顺 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
Platform: | Size: 3544064 | Author: 刘加东 | Hits:

[hardware design] idwt

Description: Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse CPU Usage: 1435 ms
Platform: | Size: 2048 | Author: farrokh | Hits:

[Other] ECOP

Description: 关于verilog语言的多周期cpu实现的方式(Multi cycle CPU implementation)
Platform: | Size: 637952 | Author: changes | Hits:

[Other] RSIC

Description: 包含控制部分和逻辑运算部分的精简CPU，适合verilog的初学者(Ti's a CPU which contain the part of chontrol and Arithmetic logic,it's approximate for people who contact veriolg with short time)
Platform: | Size: 5292032 | Author: emmm.. | Hits:

[VHDL-FPGA-Verilog] uart_design

Description: UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
Platform: | Size: 547840 | Author: 沐羽1996 | Hits:

[VHDL-FPGA-Verilog] cpu_me

Description: 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom(Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom)
Platform: | Size: 68608 | Author: 王乐 | Hits:

[VHDL-FPGA-Verilog] soc_sram_func

Description: 利用verilog编写的32位 MIPS指令集CPU，sram接口，已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)
Platform: | Size: 671744 | Author: DGP1997 | Hits:

[Education soft system] Domain Specific Hardware Accelerators: Vector Processing Units

Description: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are implemented in Bluespec System Verilog: CPU RAM Bus Vector Processor CPU A minimal 2 stage pipelined inorder processor. Vector Processor A vector processor capable of: Vector Negation (int8, int16, int32, float32) Vector Minima (int8, int16, int32, float32)
Platform: | Size: 3301613 | Author: nalevihtkas | Hits:
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